Press release: EXCELLERAT to Showcase Cutting-Edge Technologies at Automotive Testing Expo 2024

Stuttgart, Germany – The EXCELLERAT P2 project is pleased to announce its participation in the Automotive Testing Expo 2024, the world’s leading international expo for automotive testing, development, and validation technologies. The event will take place from June 4-6, 2024, at Messe Stuttgart, Germany.

Insights from the Austrian-Slovenian HPC Meeting 2024

The Austrian-Slovenian HPC Meeting (ASHPC24) took place from June 10 13, 2024, in Grundlsee, Austria. This annual gathering has become a cornerstone for scientists and technicians in the high-performance computing (HPC) community, providing a platform to discuss the latest advancements and applications in HPC technology.

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Exploring the Future of Automotive Testing: Industry-Academia Collaboration at Automotive Testing Expo

The Automotive Testing Expo Europe took place on June 4-6 in Stuttgart, featuring a new Industry-Academia Collaboration Area. This zone was designed to foster connections between the automotive industry and academic institutions, aiming to boost market competitiveness and highlight emerging talent. The goal was to encourage collaborations that drive innovation and progress.

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EXCELLERAT P2 shines at ISC High Performance 2024

From 12-16 May in Hamburg, ISC High Performance 2024 brought together more than 3,000 attendees from 51 countries, focusing on HPC, AI, and Quantum Computing. Highlights included Sophia Honisch (HLRS) introducing EXCELLERAT P2, showcasing HPC solutions for engineering challenges, and Dennis Grieger (HLRS) presenting advancements in in-situ visualization at WOIV’24.

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Explore our flyers, deliverables, and more

Success Story: In situ VR visualisation of Nek5000 simulations with Vistle

Nek5000 cases that use Exascale level performance compute data on very large grids. Writing this data to disk frequently becomes a major run time bottleneck, while handling all the data on disk comes with its own challenges. With increasing data sizes and complexity analysing the usually 3D data with conventional 2D methods becomes even harder. Running large simulations is also costly, therefore errors should better be identified rather sooner than later.

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Success Story: Running AVBP Industrial code on Arm architectures

With the diversification of the micro-processor catalogue for High-Performance systems, porting and evaluating software performance on Arm-based architectures has become an imperative step for code developers. For core performance to multi-node scalability, real application benchmarks remain elusive. Given the myriad of Arm flavours available, a comprehensive real case benchmark would give developers and users a first look for the future usage of the European Processor Initiative (EPI) and Arm-based leadership class systems.
In collaboration with Arm Ltd., CERFACS has performed a first benchmark using the AVBP code, a state-of-the-art Navier Stokes solver on unstructured grids for reactive compressible flows written in Fortran and based on MPI for parallelism.

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